Projects

Active Projects

    • I am actively seeking new opportunities to embark on an exciting journey in my new country.
    • I am in the process of updating my Github repository with the projects I have completed.
    • I am eager to pursue advanced certifications that will enhance my skills and add value to my resume.

Professional Project Experience

  • Sep 2022 - Dec 2022
    GMR Receiver
    Project Manager and Applied Researcher and Developer

    • Implemented support for all voice, IP, and SMS channel types in the protocol.
    • Developed and integrated a Fast Viterbi decoder and LDPC decoder into the system.
    • Created a system capable of multichannel receiving.
    • Designed and implemented a synchronized communication framework between the FPGA and GPU for seamless data exchange.
  • Mar 2022 - Sep 2022
    Adaptive Receiver
    Project Manager and GPU Developer
    • Implemented wideband Timing Recovery specifically for OQPSK signals.
    • Developed and integrated a Fast Reed Solomon Decoder, TPC Decoder, convolutional interleaver into the system on GPU.
    • Created a Real-time player for MPEG2 within the application.
  • May 2018 - Dec 2021
    GPU Based SDR (100M Symbol Rate)
    Project Manager, GPU Developer and System Designer
    • Developed an Online Software Defined Radio (SDR) capable of supporting high symbol rates up to 100 MSymbol/Sec through a PCI-express connection.
    • Created an Offline SDR system that efficiently processes recorded signal files. Designed and optimized a Timing Recovery algorithm that is 200 times faster than the best Intel CPUs.
    • Implemented support for various modulations, including BPSK, QPSK, 8PSK, 16APSK, 32APSK, 16QAM, 64QAM, OQPSK, 2FSK, and 4FSK.
    • Released the First Version in May 2019, supporting the PSK modulation family with a symbol rate of 10M.
    • Initiated the development of the Second Version in Dec 2020, targeting a symbol rate of 20M.
    • Achieved impressive milestones, such as 500M symbol/sec Timing Recovery and 2G PLL (Phase-Locked Loop).
    • Implemented the system on GTX-1080TI hardware for optimal performance and efficiency.
  • Jan 2021 - Oct 2021
    DVBS,DVBS2, and DVBS2X Satellite Receiver
    Project Manager, System Designer, FPGA and GPU Developer
    • Utilized a powerful combination of FPGA and GPU devices to enhance system performance.
    • Achieved high-rate interaction between the FPGA and GPU components for efficient data processing.
    • Implemented an optimized Offset Min-Sum decoder to improve decoding accuracy and efficiency.
    • Supported VL-SNR signals and Time Slice mode for enhanced signal processing capabilities.
    • Accommodated a maximum bitrate of 400 Mb/sec to handle high-speed data transmission.
    • Supported both video and IP signals for versatile data processing and communication.
    • Developed a robust system capable of multichannel receiving to handle multiple simultaneous signals effectively.
  • Apr 2020 - Jan 2021
    Deep Learning-based Automatic Modulation Recognition
    Project Manager, AI-System Designer, Python Developer
    • Employed a combination of Deep Learning-based methods and feature-based methods for enhanced accuracy and robustness.
    • Designed and developed a user-friendly interface to ensure ease of use and accessibility.
    • Conducted comprehensive testing using both synthesized signals and real-world signals to validate and optimize the system for industrial applications.
    • Supported a wide range of modulation schemes, including MPSK (2, 4, 8), MAPSK (16, 32, 64), MQAM (16, 32, 64), OQPSK, MFSK (2, 4), MSK, PI/2-DBPK, and PI/4-SQPSK.
    • Demonstrated exceptional robustness against fading effects, ensuring reliable symbol classification even at lower Signal-to-Noise Ratio (SNR) levels that surpass the capabilities of the human eye in classification by constellation.
    • Developed advanced symbol classification techniques that outperform traditional synchronization methods, ensuring accurate symbol export even in situations where signal parameters are known.
  • Dec 2019 - Dec 2020
    64 Channel Satellite Receiver
    Project Manager, FPGA Designer, CUDA Developer
    • Implemented the Physical Layer and Data Link Layer components for the target system.
    • Developed a Fast Turbo Decoder for efficient data decoding.
    • Achieved data block decoding speeds 200 times faster than the best Intel CPUs.
    • Enabled parallel processing of multiple data blocks, allowing for simultaneous execution of different tasks.
    • Implemented various key functionalities on the FPGA, including DDC, BaseBand Filter, Power Normalizer, Gain Controller, Matched Filter, Timing Recovery, and Phase Locked Loop.
    • Implemented important blocks on the GPU, including Phase Offset Estimation and Compensation, De-mapper, SNR Measurement, De-interleaver, Turbo Decoder, Descrambler, and other related components.
  • July 2018 - Oct 2018
    Interference Reduction
    Adviser, FPGA Developer
    • Successfully achieved a remarkable 40 dB reduction in interference signal power, allowing for effective recovery of the original signal.
    • Demonstrated robustness against sweep frequency interference, ensuring reliable signal reception even in challenging environments.
    • Designed a sophisticated system controller to efficiently manage and control adaptive filters, optimizing signal processing performance.
    • Implemented the entire system on FPGA using System Generator, leveraging the capabilities of hardware acceleration for enhanced efficiency and real-time processing.
  • Jan 2018 - May 2018
    Spread-Spectrum Radio Link
    FPGA Developer
    • Designed and implemented a tailored data link layer specifically optimized for the proposed physical layer, ensuring seamless and efficient communication.
    • Utilized turbo coding techniques to enhance error detection and correction capabilities, improving the overall reliability of the system.
    • Implemented a robust scrambling and interleaving mechanism to mitigate potential errors and enhance data integrity during transmission.
    • Designed a reliable framing mechanism and implemented effective data synchronization techniques to optimize connection establishment and maintain a stable communication link.
  • Apr 2017 - Feb 2018
    Automatic Modulation Recognition
    C++ Developer, System Designer in MATLAB
    • Designed a feature-based Automatic Modulation Recognition (AMR) system utilizing probabilistic features extracted from signals. This approach allows for effective modulation classification based on distinctive signal characteristics.
    • Implemented a practical AMR system using a heuristic conditional tree approach. This system enables accurate and efficient modulation recognition in real-world scenarios.
    • Developed a real-time system capable of estimating modulation type, symbol rate, and modulation index from incoming signals. This system provides timely and accurate information about the modulation parameters for further processing.
    • Implemented a Gaussian Mixture Model (GMM) based Frequency-Shift Keying (FSK) analysis method for tracking both regular and customized FSK signals. This approach allows for robust FSK signal analysis and tracking in various environments.
    • Estimated frequency offset and timing errors to compensate for inaccuracies in the demodulation system. By accurately estimating and compensating for these errors, the system achieves improved demodulation performance and signal fidelity.
  • Feb 2017 - Nov 2017
    MonoPulse
    FPGA Developer using VHDL
    • Designed a MonoPulse system with adaptive parameters that can adjust based on the Signal-to-Noise Ratio (SNR) and antenna specifications. This adaptive approach allows for optimal performance in varying conditions.
    • Implemented a MonoPulse acquisition system, enabling accurate and efficient acquisition of signals using the MonoPulse technique.
    • Developed estimation algorithms to accurately estimate relevant parameters in the MonoPulse system, such as angle of arrival or signal strength.
    • Implemented various algorithms and state machines for the blanker and main antenna components of the MonoPulse system. These algorithms and state machines ensure efficient and reliable operation of the system.
  • Feb 2017 - Jun 2017
    MultiChannel SDR
    FPGA Developer
    • Designed shared Timing Recovery, Phase-Locked Loop (PLL), and Matched Filter blocks for an eight-channel system with a 1GHz bandwidth. These blocks ensure accurate timing synchronization and efficient signal processing across all channels.
    • Employed FPGA system design techniques to optimize resource utilization, maximizing the efficiency and performance of the system. This includes efficient allocation and sharing of FPGA resources to minimize resource usage while maintaining functionality.
    • Implemented resource sharing between channels processing blocks, enabling efficient sharing of common resources among multiple channels. This approach reduces resource redundancy and improves overall system efficiency.

University Project Highlights

PhD

  1. Sep 2017– 2023
    PhD. in Electrical Engineering, Communication Systems
    School of Electrical Engineering, Amirkabir University of Technology
    Supervisors: Dr. Hamid Sheikhzadeh, Dr. Hamzeh Beyranvand
    Abstract

MSc

  1. Sep 2014– Sep 2016
    M.Sc. in Electrical Engineering, Communication Systems
    School of Electrical Engineering, Amirkabir University of Technology
    Supervisor: Dr. Hamid Sheikhzadeh, Advisor: Dr. Vahid Pourahmadi
    Abstract

BSc

  1. Sep 2010– Sep 2014
    B.Sc. in Electrical Engineering, Electronics
    School of Electrical Engineering, Shahid Rajaee University
    Supervisors: Dr. Nasour Bagheri
    Abstract